Product
Aegis
A fully open-source FPGA, from the silicon up.
Fabric generation, synthesis, place-and-route, bitstream packing, simulation, and tapeout live in one project. From HDL to GDS, nothing is behind a proprietary wall.
git clone https://git.lilithsemi.com/LilithSemi/aegis.gitWhy it exists
The pieces existed. The stack did not.
Open-source FPGA efforts have made huge strides: bitstream formats reverse engineered, open fabrics generated, commercial chips with open toolchains. Each project tackles a piece of the puzzle.
Aegis is the full stack, end to end, in one project, designed from the ground up for open source. It generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape the fabric itself out to a foundry through open PDKs and shuttle services like wafer.space.
How it works
From HDL to GDS
- 01
Generate the device
A parameterized fabric with LUT4, BRAM, DSP, SerDes and clock management tiles, generated by ROHD as synthesizable SystemVerilog, with the chip database and techmap alongside.
- 02
Synthesize and place
Yosys maps a Verilog design onto Aegis cells, then nextpnr places and routes it on the fabric.
- 03
Pack, simulate, tape out
Pack the routed design into a bitstream and simulate it cycle by cycle, then tape the fabric itself out to a foundry through open PDKs.
What's inside
What the project gives you
The whole stack in one project
Fabric generation, synthesis, place-and-route, bitstream packing, simulation and tapeout live side by side, designed for each other from the start.
Real devices, taped out
Aegis Luna 1 targets GF180MCU through wafer.space, and Aegis Terra 1 targets Sky130. Both tape out through open PDKs.
A complete toolchain per device
Yosys synthesis, nextpnr place-and-route, bitstream packing and simulation, wrapped per device and scriptable end to end.
Yours to build
Nix flakes, Docker images and Debian packages. Build the IP, the toolchain, or a full tapeout for fab submission with one command.
Also from Lilith Semi
One workflow, start to finish
Chock, Aegis, and Harbor. One for the agent that writes your code, one for the FPGA it runs on, one for the libraries it builds with.
Contact
Taping out open silicon?
Tell us what you are building and which device or flow you need. We will come back with questions and next steps.